 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CXA7000R LCD Driver Description The CXA7000R is a driver IC developed for use with Sony polycrystalline silicon TFT LCD panels. It supports 10-bit digital input, and the input data is analog demultiplexed into 6 phases and output. The CXA7000R can directly drive an LCD panel, and the VCOM setting circuit and precharge pulse waveform generator are also on-chip. Features * Supports 10-bit input * Supports signals up to XGA * Low output deviation by on-chip output offset cancel circuit * On-chip timing generator with ECL * VCOM voltage generation circuit * Precharge pulse waveform generation circuit Applications LCD projectors and other video equipment Absolute Maximum Ratings (VSS = 0V) * Supply voltage VCC 16 V VDD 5.5 V * Operating temperature Topr -20 to +70 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 1250 mW Recommended Operating Conditions * Supply voltage VCC 15.0 to 15.5 VDD 4.75 to 5.25 * Operating temperature Topr -20 to +70 64 pin LQFP (Plastic) V V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E01821A22 CXA7000R Block Diagram VCOM_OFST F/H_CNT VREF_O SL_DAT SID_LV PRG_LV SID_OUT VREF_I DIRC GND GND 48 47 46 45 44 43 42 PRG PS 41 40 39 38 37 36 35 VCC15 VDD5 34 33 TEST 49 STATUS 50 SID_Gen. Vref Gen. Line inv. VCOM_Gen. VCOM_OUT 32 PVCC 31 SH_OUT1 D_IN9 51 D_IN8 52 Offset Cancel 30 NC 29 SH_OUT2 Line inv. D_IN7 53 D_IN6 54 D_IN5 55 S/H S/H S/H Offset Cancel 28 NC 27 SH_OUT3 S/H S/H S/H Line inv. Offset Cancel 26 GND 25 PGND S/H S/H S/H GND 56 D/A GND 57 D_IN4 58 S/H S/H S/H S/H S/H S/H Line inv. Offset Cancel 24 PGND 23 GND 22 SH_OUT4 D_IN3 59 D_IN2 60 D_IN1 61 D_IN0 62 MCLK 63 MCLKX 64 TG FRP CAL_PLS Offset Cancel Control Line inv. Offset Cancel S/H S/H S/H Line inv. Offset Cancel 21 NC 20 SH_OUT5 19 NC 18 SH_OUT6 17 PVCC 1 FRP 2 SHST 3 POSCNT0 4 POSCNT1 5 POSCNT2 6 POSCNT3 7 SHTEST 8 GND 9 GND 10 NC 11 SIG.C 12 SIG_OFST 13 CAL_L 14 CAL_H 15 GND 16 DCFBOFF -2- CXA7000R Pin Description Pin No. Symbol I/O Standard voltage level Equivalent circuit VDD 50k Description 1 FRP I High: 2.0V Low: 0.8V 192 1 LCD panel AC drive inversion timing input. High: inverted Low: non-inverted See the Timing Chart. Internal sample-and-hold timing circuit reset pulse input. This pin is also used as the offset cancel level insertion timing input. A reset is applied to the internal timing generator at the falling edge. Output phase adjustment. The output phase is adjusted in MCLK period units when SL_DAT is high, and in 1/2 MCLK period units when SL_DAT is low. GND VDD 50k 2 SHST I High: 2.0V Low: 0.8V 192 2 GND VDD 3 4 5 6 POSCNT0 POSCNT1 POSCNT2 POSCNT3 3 50k 192 I High: 2.0V Low: 0.8V 4 5 6 GND VDD 30k VCC 20 11 SIG.C I 1 to 5.0V 11 Signal center voltage (inversion folded voltage) adjustment input. The SH_OUT output center voltage can be adjusted in the range from 7.0 to 8.0V. GND VDD 30k VCC 10 12 SIG_OFST I 0 to 5.0V 12 GND Output signal offset adjustment from signal center voltage. The SH_OUT output 100% white level (at 3FF input) voltage can be adjusted in the range from 0 to 1V from the center voltage. VCC 40 1k 145 13 14 GND 13 14 CAL_L CAL_H I/O 3.0 to 6.0V 9.0 to 12.0V Level output for canceling the offset between channels. Connect the CAL_L and CAL_H, between ICs when using two CXA7000R. -3- CXA7000R Pin No. Symbol I/O Standard voltage level Equivalent circuit VDD 24k 24k 145 16 Description 16 DCFBOFF I GND Offset cancel function off. Normally connect to GND to use with the offset cancel function on. High (offset cancel function off) when open. GND PVCC 18 18 20 22 27 29 31 300 20 22 27 29 31 SH_OUT6 to SH_OUT1 O 1.5 to 13.5V 300 Demultiplexed output of AC inverse driven video signals. Can be connected directly to the LCD panel. GND VCC 80 100k 500 145 33 500 33 VCOM_OUT O 5.0 to 8.0V LCD panel common voltage output. Can be set in the range from the SH_OUT center potential Vsig.c to Vsig.c - 2V by VCOM_OFST. GND VDD 2k VCC 80 34 VCOM_OFST I 0 to 5.0V 34 100 GND LCD panel common voltage adjustment. VCOM_OUT can be set in the range from the SH_OUT center potential Vsig.c to Vsig.c - 2V by inputting 0 to 5V. VCC 100k 0.2p 145 36 100k 0.2p GND 36 SID_OUT O 1.5 to 13.5V Precharge waveform output. These pins cannot directly drive the LCD panel, so input to the LCD panel with an external buffer. -4- CXA7000R Pin No. Symbol I/O Standard voltage level VDD Equivalent circuit VCC 29 Description 37 38 PRG_LV SID_LV I 1.0 to 5.0V 50k 37 50k 38 GND Precharge level setting. Adjusts the SID_OUT and SID_OUTX output potential. PRG_LV is reflected when the PRG input pin (Pin 60) is high, and SID_LV is reflected when PRG is low. VDD 100k VCC 10k 39 PRG I High: 2.0V Low: 0.8V 39 50 GND VDD 70 10 Timing pulse input for switching the Pin 36 output levels. (See PRG_LV (Pin 37) and SID_LV (Pin 38).) 44 VREF_I I 3.2V 44 1k 280 GND 33.3k Internal D/A converter reference voltage input. Normally connect directly to VREF_O. VDD 2k 45 VREF_O O 3.2V 20 45 20k 12.4k GND VDD 50k Reference voltage output. Normally connect directly to VREF_I, and connect to GND through a 0.5 to 1.0F capacitor. 46 F/H_CNT I High: 2.0V Low: 0.8V Open: Low 192 46 200k GND SH_OUT output timing selection. High: SH_OUT1 to SH_OUT3 and SH_OUT4 to SH_OUT6 are output at different timing. Low: SH_OUT1 to SH_OUT6 are output at the same timing. VDD 50k 47 DIRC I High: 2.0V Low: 0.8V 192 47 GND Scan direction setting. High: output as a time series in ascending order of output pin symbol (in order from SH_OUT1 to SH_OUT6) Low: output in descending order -5- CXA7000R Pin No. Symbol I/O Standard voltage level Equivalent circuit VDD 50k Description 48 SL_DAT I High: 2.0V Low: 0.8V Open: Low 192 48 200k GND Digital input mode switch setting. High: when using master/slave mode two CXA7000R. Low: when using normal mode one CXA7000R. VDD 200k 50k 50 STATUS I High: 2.0V Low: 0.8V 192 50 GND Master/slave setting when using two CXA7000R. High: master IC. Offset cancel level is output. Low: slave IC. This pin is left open (high) when using one CXA7000R. VDD 51 to 55 58 to 62 50k D_IN9 to D_IN0 I High: 2.0V Low: 0.8V 192 51 to 55 58 to 62 GND Digital data input. VDD 63 64 MCLK MCLKX I PECL differential (amplitude 0.4V or more between VDD to 2V) or TTL input 140k 1k 63 1k 64 60k GND 8k 140k 100 60k Dot clock input. PECL differential input or TTL input. For TTL input, input to MCLK and connect MCLKX to GND through a capacitor. VDD 70k 42 PS I 5V 42 180k GND 30 Test. Normally connect to VDD. 24, 25 PGND 17, 32 PVCC 35 43 VCC15 VDD5 GND 15.5V 15.5V 5V -6- Power GND. Power VCC. 15V power supply. 5V power supply. CXA7000R Pin No. Symbol I/O Standard voltage level GND Equivalent circuit Description 8, 9, 15, 23, 26, GND 40, 41, 56, 57 10, 19, 21, 28, NC 30 GND. NC. These pins are not connected to anything. VDD 20k 250k 20k 20k 20k 7 SHTEST I 2.5V 192 7 250k GND 10 10 Test. Leave open. VDD 1 2k 192 49 49 TEST O 1.7 to 3.2V 20 GND DAC output monitor test. Normally connect to VDD. -7- CXA7000R Electrical Characteristics Measurement Circuit VDD 47p VCC 1 48 VDD 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCOM_OUT A SID_OUT F/H_CNT VREF_O PRG_LV SL_DAT VREF_I SID_LV DIRC VDD5 GND GND PRG A VCC15 VCOM_OFST PS TEST STATUS D_IN9 D_IN8 D_IN7 D_IN6 D_IN5 GND GND D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 MCLK MCLKX PVCC SH_OUT1 NC SH_OUT2 NC SH_OUT3 GND PGND PGND GND SH_OUT4 NC SH_OUT5 NC SH_OUT6 PVCC 270p 270p 270p 270p 270p 270p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A VCC POSCNT0 POSCNT1 POSCNT2 POSCNT3 SHTEST SIG_OFST CAL_L DCFBOFF FRP SHST GND GND NC CAL_H SIG.G GND VCC 15.5V VDD 5V -8- CXA7000R Electrical Characteristics No. 1 2 3 4 Item Digital input resolution Digital input setup time Digital input hold time MCLK input frequency range 1 MCLK input frequency range 2 VREF_I input voltage range Symbol n TS TH fMCLK1 SHST and D_IN[9:0] minimum setup time relative to MCLK input. SHST and D_IN[9:0] minimum hold time relative to MCLK input. SL_DAT: 5V; maximum frequency at which the internal timing generator and D/A converter operate normally. SL_DAT: 0V; maximum frequency at which the internal timing generator and D/A converter operate normally. VREF_I input voltage range at which the D/A converter operate normally. Measure the VREF_O (Pin 45) voltage. VOUT1 Measurement points Measurement conditions Min. Typ. Max. Unit -- 2 3 60 10 -- -- -- -- -- -- bit ns ns 100 MHz 5 6 7 8 fMCLK2 VVREF_I 30 2.7 3.1 -- 3.2 3.2 4.5 80 3.5 3.3 4.64 MHz V V V V VREF_O output VVREF_O voltage range SH_OUT amplitude SH_OUT minimum amplitude VSHOUTp-p Measure the SH_OUT1 voltage 4.39 difference at D_IN[9:0]: 000h and 3FFh. Lower the VREF_I voltage and adjust the amplitude; minimum amplitude at which SH_OUT1 can be output at D_IN[9:0]: 000h and 3FFh. 3.9 9 VOUTMINp-p VOUT1 -- -- 10 SH_OUT slew rate SROUT VOUT1 to VOUT6 Load capacitance = 270pF; measure slew rate at 10 to 90% of output waveform rise and fall when D_IN[9:0] 150 is varied from 000h to 3FFh and from 3FFh to 000h. Minimum voltage at which sampleand-hold outputs VOUT1 to VOUT6 can be output. Maximum voltage at which sampleand-hold outputs VOUT1 to VOUT6 can be output. Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 200h. Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 000h or 3FFh. Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 200h. (when using two CXA7000R) 1.5 150 -- V/s SH_OUT 11 minimum output voltage SH_OUT 12 maximum output voltage VMIN VOUT1 to VOUT6 VOUT1 to VOUT6 VOUT1 to VOUT6 VOUT1 to VOUT6 -- -- V VMAX -- -- 13.5 V Output deviation 13 between DOUT1 channels 1 Output deviation 14 between DOUT2 channels 2 Output deviation 15 DIC1 between ICs 1 -- 3 10 mVp-p -- 10 40 mVp-p VOUT1 to VOUT6 -- 10 -- mVp-p -9- CXA7000R No. Item Measurement Symbol points VOUT1 to VOUT6 VSID_LV VSID VPRG_LV VSID Measurement conditions Value obtained by subtracting minimum VOUT1 to VOUT6 value from maximum VOUT1 to VOUT6 value at D_IN[9:0]: 000h or 3FFh. (when using two CXA7000R) PRG: 0V; measure VSID_LV and VSID at FRP: 0V, and VSID_LV at FRP: 5V. Calculate as ASID1 = VSID/VSID_LV. PRG: 5V; measure VPRG_LV and VSID at FRP: 0V, and VPRG_LV at FRP: 5V. Calculate as ASID2 = VSID/VPRG_LV. Load capacitance = 47pF, PRG: 0V; input a repeating high/low pulse to FRP (Pin 1), and apply DC input voltage so that VSID is 4V/10V. Measure slew rate at 10 to 90% of output waveform rise and fall. VOUT1 center voltage when SIG.C (Pin 11) is varied from 0 to 5V. D_IN[9:0]: 3FFh, FRP: 0V; value obtained by subtracting VOUT1 from VOUT1 center voltage when SIG_OFST (Pin 12) is varied from 0 to 5V. VCOM_OUT voltage when VCOM_OFST (Pin 34) is varied from 0 to 5V. IDD = IVDD ICC = IVCC1 + IVCC2 GND (Pin 42), ICC = IVDD + IVCC1 + IVCC2 VVREF_I = 3.2V VVREF_I = 3.2V Min. Typ. Max. Unit Output deviation 16 DIC2 between ICs 2 SID output gain 1 SID output gain 2 -- 20 -- mVp-p 17 ASID1 1.9 2 2.1 times 18 ASID2 1.9 2 2.1 times 19 SID output slew rate SRSID VSID 27 50 -- V/s 20 Signal center VSIG adjustable range VOUT1 7 -- 8 V SH_OUT offset 21 VSIGOFST adjustable range 22 23 24 VCOM VCOM adjustable range VDD current consumption VCC current consumption IDD ICC VOUT1 0 Vc - 2.5 -- -- -- 1 V VCOM IVDD IVCC1 IVCC2 IVDD IVCC1 IVCC2 -- -- -- 52 18 Vc -- -- V mA mA Current consumption in 25 IPS power saving mode 26 27 Differential linearity error DLE -- 28 -- mA -0.5 -1.5 0.7 0.4 LSB LSB Integral linearity ILE error - 10 - CXA7000R Description of Operation The flow of internal operations is described below. The digital signals input to D_IN0 to D_IN9 are internally D/A converted into approximately 1.5V (at VREF_I: 3.2V) analog signals. After that, the signal that has been demultiplexed into 6 phases is amplified by a factor of three times, inverted at the signal center potential according to FRP and output. , The output level relative to the digital input changes according to the following settings. A: SIG_OFST voltage B: VREF_I voltage VCC C: SIG.C voltage B A A 1023 C B 512 0 Digital IN SH_OUT Signal Center GND 1. Digital input block The CXA7000R can be set to master/slave mode, single mode and left/light inversion. This makes it possible to support various systems. In master/slave mode, the even and odd data is internally selected respectively and input to the D/A converter. 2. D/A converter block The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a maximum 1.5Vp-p with respect to input data of 000h to 3FFh. 3. Sample-and-hold (S/H) block The D/A converter outputs are input to the sample-and-hold blocks, respectively. The signals are converted from time series signals into 6-phase cyclic parallel signals by the sample-and-hold group which is appropriately controlled by the internal timing generator. For forward scan, the signals are output in the ascending order of SH_OUT1, SH_OUT2, SH_OUT3 ... SH_OUT6. For reverse scan, this order is inverted and the signals are output in descending order. Connect the signals to the LCD panel according to the order used. The timing of each sample-and-hold pulse is shown on the following pages. These pulses are not output and are used only inside the IC. - 11 - CXA7000R Master/slave mode D_IN1 10bit D_IN[9:0] D D D Selector L H D D_IN2 DAC DAC_O S/H STATUS MCLK MCLK/2 D_IN[9:0] MCLK D_IN1 D_IN2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 0 1 2 3 1 4 5 3 6 7 5 8 9 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 9 11 13 15 17 19 21 23 25 27 DAC_O DIRC: H SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 F/H_CNT: L SH3A_1_6 F/H_CNT: H SH3B_1_3 SH3B_4_6 DIRC: L SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 F/H_CNT: L SH3A_1_6 F/H_CNT: H SH3B_1_3 SH3B_4_6 1 3 CH1 to CH6 simultaneous output timing CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing CH1 to CH6 simultaneous output timing CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing - 12 - CXA7000R Single mode DAC 10bit D_IN[9:0] D D D_IN1 D D_IN2 DAC_O S/H MCLK D_IN[9:0] MCLK D_IN1 D_IN2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -2 -3 -1 -2 0 -1 1 0 2 1 3 2 4 3 5 4 6 5 7 6 8 7 9 8 10 9 11 10 12 11 13 12 DAC_O DIRC: H SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 F/H_CNT: L SH3A_1_6 F/H_CNT : H SH3B_1_3 SH3B_4_6 DIRC: L SH1_1 SH1_2 SH1_3 SH1_4 SH1_5 SH1_6 SH2_1_3 SH2_4_6 F/H_CNT: L SH3A_1_6 F/H_CNT: H SH3B_1_3 SH3B_4_6 -1 0 1 CH1 to CH6 simultaneous output timing CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing CH1 to CH6 simultaneous output timing CH1 to CH3 simultaneous output timing CH4 to CH6 simultaneous output timing - 13 - CXA7000R 4. Timing generator (TG) block The internal timing generator operates by one pair of differential clock inputs (MCLK, MCLKX) and a horizontal sync signal input (SHST), and generates the timing pulses needed by the demultiplexer block, dot inversion control pulse and output deviation cancel circuit. The various operating modes can be designated by the pin settings. The SHST and FRP inputs should satisfy the relationship shown in the figure below with the MCLK and MCLKX input period as 1clk. SHST FRP 30clk or more 1s or more The CXA7000R can select various operating modes according to the timing generator block settings. These settings are described below. * SL_DAT (Pin 48) Operation mode selection. Master/slave mode is selected which is common with digital input of two ICs when set to high level, and single mode is selected with one IC when set to low level. In case of the former, connect 10-bit input as short as possible between two ICs and select which data of odd or even is obtained by STATUS (Pin 50). * DIRC (Pin 47) Scan direction settings. Output is ascending order when DIRC is set to high level, and inverted to descending order (SH_OUT1 to SH_OUT6) when set to low level. Also, the output is varied as shown below in combination with STATUS (Pin 50). D_IN[9:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SL_DAT: L DIRC: L SH_OUT1: 6 SH_OUT2: 5 SH_OUT3: 4 SH_OUT4: 3 SH_OUT5: 2 SH_OUT6: 1 DIRC: L SH_OUT1: 11 SH_OUT2: 9 SH_OUT3: 7 SH_OUT4: 5 SH_OUT5: 3 SH_OUT6: 1 SH_OUT1: 12 SH_OUT2: 10 SH_OUT3: 8 SH_OUT4: 6 SH_OUT5: 4 SH_OUT6: 2 - 14 - DIRC: H SH_OUT1: 1 SH_OUT2: 2 SH_OUT3: 3 SH_OUT4: 4 SH_OUT5: 5 SH_OUT6: 6 DIRC: H SH_OUT1: 2 SH_OUT2: 4 SH_OUT3: 6 SH_OUT4: 8 SH_OUT5: 10 SH_OUT6: 12 SH_OUT1: 1 SH_OUT2: 3 SH_OUT3: 5 SH_OUT4: 7 SH_OUT5: 9 SH_OUT6: 11 SL_DAT: H STATUS: L STATUS: H CXA7000R * F/H_CNT (Pin 46) SH_OUT output timing phase setting. When set to low level, all SH_OUT outputs are output at the same timing. When set to high level, SH_OUT1 to SH_OUT3 and SH_OUT4 to SH_OUT6 are output at phases offset by 1/2 clock period from each other. SH_OUT4 to 6 SH_OUT4 to 6 SH_OUT1 to 3 SH_OUT1 to 3 GND GND F/H_CNT: L F/H_CNT: H * Output phase setting The phase of each SH_OUT output can be adjusted by POSCNT[3:0] (Pins 3 to 6). The phase can be set in 16 ways by 4-bit digital input. The output phase shifts backward by the clock period units when SL_DAT is high or 1/2 clock period units when SL_DAT is low each time this setting is increased by one bit. - 15 - CXA7000R 5. Calibration level generator block The CXA7000R has a built-in offset cancel circuit and generates the reference with a calibration level generator in order to minimize the deviation between channels at the center level. The 200h output level is generated at both the AC output high and low sides respectively when STATUS (Pin 50) is high level, and these levels are DC output from CAL_H and CAL_L and at the same time, these are used internally. When STATUS (Pin 50) is low level, CAL_H and CAL_L are input pins and the external offset cancel level is input. The 200h data is forcibly inserted into the video signal while the video blanking period SHST pulse is low level, and feedback is applied so that the output levels of all SH_OUT channels conform to CAL_H and CAL_L during this period. SHST Video signal replacement period FRP 200ns CAL_PLS (internal pulse) 200h SH_OUT Signal center 200h 000h Offset cancel operation 000h Delayed by sample-and-hold 6. SID signal generator block This circuit generates the precharge signal waveform used by the LCD panel. The voltage input from PRG_LV (Pin 37) and SID_LV (Pin 38) is switched by the PRG pulse (Pin 39). The PRG_LV voltage is selected when PRG is high, and the SID_LV voltage is selected when PRG is low. This signal is then further amplified by a factor of two times and folded by the FRP pulse. The folded center voltage is the SH_OUT center voltage (voltage set by the SIG.C pin). SID_OUT (Pin 36) is inverted when FRP is high, and non-inverted when FRP is low. SID_OUT cannot directly drive the precharge signal input of the LCD panel, so they should be connected via a buffer having sufficient current supply capability. 7. VCOM potential generator block This block sets the DC common potential for the LCD panel. VCOM_OFST (Pin 33) sets the deviation relative to the SH_OUT center potential, which is set by SIG.C. - 16 - CXA7000R Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, Ta = 25C) VREF_I voltage vs. SH_OUT voltage white-black amplitude 4.8 SH_OUT white-black amplitude voltage [V] Input data vs. SH_OUT voltage 14 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 3.9 3.8 2.8 SH_OUT voltage [V] 12 FRP = High 10 8 6 FRP = Low 4 2 0 000h 2.9 3.0 3.1 VREF_I voltage [V] 3.2 3.3 SIG.C voltage vs. SH_OUT center voltage 9.0 8.5 SH_OUT center voltage [V] SIG_OFST voltage vs. SH_OUT voltage 12 SH_OUT voltage [V] 8.0 7.5 7.0 6.5 6.0 5.5 5.0 2.5 11 10 9 8 7 6 5 4 3 3.0 3.5 4.0 SIG.C voltage [V] 4.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SIG_OFST voltage [V] VCOM_OFST voltage vs. VCOM_OUT voltage 7.5 7.0 VCOM_OUT voltage [V] 6.5 6.0 5.5 5.0 4.5 0.0 1.0 2.0 4.0 3.0 VCOM_OFST voltage [V] 5.0 - 17 - CXA7000R SID_LV voltage vs. SID_OUT voltage 16 14 12 FRP = High 10 8 6 FRP = Low 4 2 0 0 1 2 SID_LV voltage [V] 3 4 PRG_LV voltage vs. SID_OUT voltage SID_OUT voltage [V] SID_OUT voltage [V] FRP = High 10 8 6 FRP = Low 4 2 0 0 1 2 PRG_LV voltage [V] 3 4 - 18 - CXA7000R Application Circuit 1 (to SVGA Panel) VDD 20k Buffer 1 DSD CXD3526GG 20k 10 10 Psig VDD 1F VDD 0.1F VDD 20k PRG 45 RGT 2 20k VDD 0.1F 47F VCOM_OUT 0.1F VCC 1 24 COM VDD PRG_LV SID_OUT F/H_CNT VREF_O VREF_I SID_LV VCC15 VCOM_OFST VDD SL_DAT 47F PVCC DIRC VDD5 GND GND VDD 10k TEST STATUS ROUT9 38 ROUT8 39 ROUT7 40 ROUT6 36 ROUT5 79 10 10 10 10 10 D_IN9 D_IN8 D_IN7 D_IN6 D_IN5 GND GND ROUT4 80 ROUT3 81 ROUT2 35 ROUT1 78 ROUT0 113 CLKOUT 28 10 10 10 10 10 10 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 MCLK MCLKX 0.1F 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PRG PS PVCC SH_OUT1 NC SH_OUT2 NC SH_OUT3 GND PGND PGND GND SH_OUT4 NC SH_OUT5 NC SH_OUT6 PVCC 0.1F 47F 1 6 1 7 Vsig1 Vsig2 Vsig3 1 5 1 3 CXA7000R 24 23 22 21 20 19 18 17 LCD Panel LCX026 1 2 Vsig4 Vsig5 Vsig6 1 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 POSCNT0 POSCNT1 POSCNT2 POSCNT3 SHTEST SIG_OFST OPEN 1F FRP 118 SHST 119 10 10 VDD 0.1F 20k 1F VDD PVCC 0.1F 20k 15.5V 15.5V 5V VCC VDD Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 19 - DCFBOFF SHST FRP SIG.C GND GND CAL_L CAL_H GND NC CXA7000R Application Circuit 2 (to XGA Panel) DSD CXD3526GG 20k 10 10 VDD VDD 20k Buffer 1 Psig VDD 1F VDD 0.1F VDD 20k PRG 45 RGT 2 20k 0.1F 0.1F 47F VCOM_OUT VCC 1 31 COM VDD F/H_CNT VREF_O PRG_LV SID_OUT VREF_I SID_LV VCC15 VCOM_OFST VDD SL_DAT 47F PVCC DIRC VDD5 GND GND VDD 10k TEST STATUS ROUT9 38 ROUT8 39 ROUT7 40 ROUT6 36 ROUT5 79 10 10 10 10 10 D_IN9 D_IN8 D_IN7 D_IN6 D_IN5 GND GND ROUT4 80 ROUT3 81 ROUT2 35 ROUT1 78 ROUT0 113 CLKOUT 28 10 10 10 10 10 10 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 MCLK MCLKX 0.1F 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PRG PS PVCC SH_OUT1 NC SH_OUT2 NC SH_OUT3 GND PGND PGND GND SH_OUT4 NC SH_OUT5 NC SH_OUT6 PVCC 0.1F 47F 1 13 Vsig11 1 3 Vsig1 Vsig3 Vsig5 1 5 1 7 CXA7000R 24 23 22 21 20 19 18 17 1 9 Vsig7 1 11 Vsig9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC SHST GND GND SHTEST CAL_L SIG.C CAL_H GND FRP FRP 118 SHST 119 10 10 SIG_OFST POSCNT0 POSCNT1 POSCNT2 POSCNT3 DCFBOFF LCD Panel LCX029 OPEN VDD VDD 1F 20k 0.1F 47F VDD F/H_CNT VREF_O SL_DAT VREF_I 0.47F 0.47F VCC VDD VDD PRG_LV SID_OUT VCOM_OFST VDD VCOM_OUT SID_LV PVCC DIRC GND GND VDD 10k TEST STATUS D_IN9 D_IN8 D_IN7 D_IN6 D_IN5 GND GND D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 MCLK MCLKX 0.1F 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PRG PS VCC15 VDD5 PVCC SH_OUT1 NC SH_OUT2 NC SH_OUT3 GND PGND PGND GND SH_OUT4 NC SH_OUT5 NC SH_OUT6 PVCC 47F 0.1F 1 14 Vsig12 1 4 Vsig2 Vsig4 Vsig6 1 6 1 8 CXA7000R 24 23 22 21 20 19 18 17 1 10 Vsig8 1 12 Vsig10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND GND FRP NC SHST SHTEST SIG.C GND VDD OPEN 20k 0.1F 0.47F VDD 0.47F 20k 0.1F PVCC 15.5V VCC 15.5V VDD 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 20 - SIG_OFST POSCNT0 POSCNT1 POSCNT2 POSCNT3 DCFBOFF CAL_L CAL_H CXA7000R Application Circuit 3 (to SXGA Panel) DSD CXD3511Q 20k 10 10 VDD VDD 20k Buffer 1 Psig VDD 1F VDD 0.1F VDD 20k PRG 161 RGT 136 20k 0.1F 0.1F 47F VCOM_OUT 2 COMR VCC 1 21 COML 32 COM VDD F/H_CNT VREF_O PRG_LV SID_OUT VREF_I SID_LV VCC15 VCOM_OFST VDD SL_DAT 47F PVCC DIRC VDD5 GND GND VDD 10k TEST STATUS R1OUT9 122 R1OUT8 121 R1OUT7 120 R1OUT6 119 R1OUT5 118 10 10 10 10 10 D_IN9 D_IN8 D_IN7 D_IN6 D_IN5 GND GND R1OUT4 117 R1OUT3 116 R1OUT2 113 R1OUT1 112 R1OUT0 111 CLKOUT 47 10 10 10 10 10 10 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 MCLK MCLKX 0.1F 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PRG PS PVCC SH_OUT1 NC SH_OUT2 NC SH_OUT3 GND PGND PGND GND SH_OUT4 NC SH_OUT5 NC SH_OUT6 PVCC 0.1F 47F 1 13 Vsig11 1 3 Vsig1 Vsig3 Vsig5 1 5 1 7 CXA7000R 24 23 22 21 20 19 18 17 1 9 Vsig7 1 11 Vsig9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 POSCNT0 POSCNT1 POSCNT2 POSCNT3 SIG_OFST FRP 157 SHST 159 10 10 DCFBOFF SHTEST CAL_L SIG.C CAL_H SHST GND GND GND FRP NC LCD Panel LCX028 OPEN VDD VDD 1F 20k 0.1F 47F VDD F/H_CNT VREF_O SL_DAT VREF_I 0.47F 0.47F VCC VDD VDD PRG_LV SID_OUT VCOM_OFST VDD VCOM_OUT SID_LV PVCC DIRC VDD5 GND GND VDD 10k TEST STATUS R2OUT9 110 R2OUT8 109 R2OUT7 108 R2OUT6 107 R2OUT5 106 10 10 10 10 10 D_IN9 D_IN8 D_IN7 D_IN6 D_IN5 GND GND R2OUT4 105 R2OUT3 104 R2OUT2 103 R2OUT1 99 R2OUT0 98 10 10 10 10 10 D_IN4 D_IN3 D_IN2 D_IN1 D_IN0 MCLK MCLKX 0.1F 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PRG PS VCC15 PVCC SH_OUT1 NC SH_OUT2 NC SH_OUT3 GND PGND PGND GND SH_OUT4 NC SH_OUT5 NC SH_OUT6 PVCC 47F 0.1F 1 14 Vsig12 1 4 Vsig2 Vsig4 Vsig6 1 6 1 8 CXA7000R 24 23 22 21 20 19 18 17 1 10 Vsig8 1 12 Vsig10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 POSCNT0 POSCNT1 POSCNT2 POSCNT3 SIG_OFST VDD OPEN 20k 0.1F 0.47F VDD 0.47F 20k 0.1F PVCC 15.5V VCC 15.5V VDD 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 21 - DCFBOFF SHTEST CAL_L SIG.C CAL_H SHST GND GND GND FRP NC CXA7000R Notes on Operation The CXA7000R has high power consumption, so be sure to take the following radiation measures. * Use four-layer substrate. * GND lines connected to Pins 8, 9, 24, 25, 40, 41, 56 and 57 should be as thick as possible. - 22 - CXA7000R Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 0.2 48 49 10.0 0.1 33 32 A 64 1 0.5 b 16 0.13 M + 0.2 1.5 - 0.1 17 (0.22) 0.5 0.2 0.1 EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.3g 0.1 0.1 b = 0.18 0.03 0 to 10 0.5 0.2 DETAIL B: PALLADIUM DETAIL A NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 P-LQFP64-10x10-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS 0.125 0.04 (11.0) - 23 - Sony Corporation |
Price & Availability of CXA7000R
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |